1. Field of the Invention
The present invention relates to an integrated circuit designing system, method and program for designing LSIs with the aid of a computer, and, more particularly, to an integrated circuit designing system, method and program for degenerating the size of simulation models for use in logic verification of the LSIs.
2. Description of the Related Art
Conventionally, in a computer-aided automated designing system of LSIs, design works are performed in conformity with design processes such as system design, function design, logic design, circuit design, layout design, design verification and mask data generation. Among these, function design includes designing a register transfer level (RT level) which determines the structure and operation inside a function block and using a logic simulator for verification of the design results. Logic design performed after the function design is gate level logic design and uses a logic simulator or timing simulator for checking of operations. To input and edit logic diagrams, a logic synthesis tool is used which automatically generates gate circuits from logic descriptions. Stated differently, in logic design, in order to compile logics described on the logic operation level into logics on the gate level and conduct a logic simulation on this gate level, logics described on the gate level are converted to basic primitives which can be executed by a simulator, to generate simulation models for simulations (see, e.g., Japanese Patent Application Laid-Open Publication Nos. 2000-358185 and 1996-87532).
However, there is a problem that, in a hardware simulator (hardware accelerator) used for logic simulations on the gate level, maximum verification model size (number of gates) which can be processed is limited and large net lists can not be handled. Also, in software simulator, as the size of the verification model becomes larger, the simulation rate is deteriorated and a file size of the generated simulation model is increased. In order to solve this problem, buffer reduction can be considered, wherein, for example, successive buffers 204-1, 204-2, . . . 204-n provided between FF 200 and FF 202 of FIG. 1A are targeted and the buffers 204-2 to 204-n are deleted as shown in FIG. 1B. However, if the buffer reduction is performed, there are problems that delay stage counts is affected and that timings are varied in a delay simulator because of different delay stage counts. Therefore, it is needed to delete the number of gates in the simulation model on the gate level, without affecting the delay stage counts.